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d a t a sh eet preliminary speci?cation file under integrated circuits, ic02 1997 jun 24 integrated circuits SAA5288 tv microcontroller with full screen on screen display (osd)
1997 jun 24 2 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 contents 1 features 1.1 general 1.2 microcontroller 1.3 display 2 general description 3 quick reference data 4 ordering information 5 block diagram 6 pinning information 6.1 pinning 6.2 pin description 7 functional description 7.1 microcontroller 7.2 80c51 features not supported 7.2.1 interrupt priority 7.2.2 off-chip memory 7.2.3 idle and power-down modes 7.2.4 uart function 7.3 additional features 7.3.1 interrupts 7.3.2 bit level i 2 c-bus interface 7.3.3 byte level i 2 c-bus interface 7.3.4 led support 7.3.5 6-bit pwm dacs 7.3.6 14-bit pwm dac 7.3.7 software adc 7.4 microcontroller interfacing 7.4.1 special function register map 7.4.2 special function registers bit description 7.5 the display 7.5.1 introduction 7.5.2 character matrix 7.5.3 page attributes 7.5.4 east/ west selection 7.5.5 national option characters 7.6 the twist attribute 7.6.1 on screen display symbols 7.6.2 language group identification 7.6.3 525-line operation 7.6.4 control characters 7.6.5 display modes 7.7 on screen display boxes 7.8 screen colour 7.9 cursor 7.10 other display features 7.11 display timing 7.12 horizontal timing 7.13 vertical timing 7.14 display position 7.15 clock generator 8 character sets 8.1 pan-european 8.2 russian 8.3 greek/turkish 8.4 arabic/english/french 8.5 thai 8.6 arabic/hebrew 9 limiting values 10 characteristics 11 characteristics for the i 2 c-bus interface 12 quality specifications 13 application information 14 emc guidelines 15 package outline 16 soldering 16.1 introduction 16.2 soldering by dipping or by wave 16.3 repairing soldered joints 17 definitions 18 life support applications 19 purchase of philips i 2 c components
1997 jun 24 3 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 1 features 1.1 general on-chip tv control tuning hardware and software compatible with saa5290, saa5291 and saa5296 single +5 v power supply rgb interface to standard decoder ics, push-pull output drive sdip52 package single crystal oscillator for display and microcontroller. 1.2 microcontroller 80c51 microcontroller core 16 kbyte mask programmed rom 256 bytes of microcontroller ram eight 6-bit pulse width modulator (pwm) outputs for control of tv analog signals one 14-bit pwm for voltage synthesis tuner control four 8-bit analog-to-digital converters (adcs) 2 high current open-drain outputs for directly driving leds etc. switchable bit or byte-oriented i 2 c-bus interface. 1.3 display single page (1024 8) on-board on screen display (osd) memory double size width and height capability for osd enhanced display features including meshing, shadowing and additional display attributes 260 characters in mask programmed rom display clock derived internally to reduce peripheral components to a minimum automatic frame output control with manual override standby mode for display hardware 525-line and 625-line display 12 10 character matrix stable display via slave synchronization to horizontal sync and vertical sync. 2 general description the SAA5288 is a microcontroller for use in televisions with an osd generator compatible with the economy teletext/tv microcontroller family (saa5290, saa5291, saa5296 etc.). tv control facilities are provided by an on-chip industry standard 80c51 microcontroller and a 1 kbyte dram is included for osd memory. hardware and software compatibility with the economy teletext/tv microcontroller family minimizes the changes required to develop a tv control function for areas where teletext is not broadcast. the device cannot acquire teletext but is based on a teletext device. therefore, throughout this document references are made to teletext especially when describing the display/osd section. the display/osd section is fully compatible with a teletext display and has all the features associated with teletext (i.e. double height/width, flash, teletext boxes, graphics, etc.). the display section is described with reference to teletext to allow software compatibility with the economy teletext/tv microcontroller family. 3 quick reference data symbol parameter min. typ. max. unit v dd supply voltage (all supplies) 4.5 5.0 5.5 v i ddm microcontroller supply current - 15 30 ma i dda analogue supply current - 815ma i ddt display supply current - 15 30 ma f xtal crystal frequency - 12 - mhz t amb operating ambient temperature - 20 - +70 c
1997 jun 24 4 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 4 ordering information 5 block diagram type number package name description version SAA5288ps/nnn sdip52 plastic shrink dual in-line package; 52 leads (600 mil) sot247-1 fig.1 block diagram. handbook, full pagewidth mgl121 port 1 reset port 0 8051 cpu 16 kbyte rom i 2 c-bus timer/ counter adc xtalin v ddm v ssd v ddd v dda xtalout oscgnd vsync hsync frame data address interrupt page ram display display timing oscillator 256 byte ram text interface port 2 p2.0 to p2.7 p3.0 to p3.7 p0.0 to p0.7 p1.0 to p1.7 port 3 pwm r, g, b, vds, cor
1997 jun 24 5 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 6 pinning information 6.1 pinning fig.2 pin configuration. handbook, halfpage SAA5288 mgl114 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 p2.0/tpwm p2.1/pwm0 p2.2/pwm1 p2.3/pwm2 p2.4/pwm3 p2.5/pwm4 p2.6/pwm5 p2.7/pwm6 p3.0/adc0 p3.1/adc1 p3.2/adc2 p3.3/adc3 v ssd p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 v ssd i.c. i.c. i.c. iref p1.5 p1.4 p1.7/sda p1.6/scl p1.3/t1 p1.2/int0 p1.1/t0 p1.0/int v ddm reset xtalout xtalin oscgnd v ddd v dda vsync hsync vds r g b rgbref p3.4/pwm7 cor v ssd frame 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
1997 jun 24 6 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 6.2 pin description table 1 sdip52 package symbol pin description p2.0/tpwm 1 port 2. 8-bit open-drain bidirectional port with alternative functions. p2.0/tpwm is the output for the 14-bit high precision pwm. p2.1/pwm0 to p2.7/pwm6 are the outputs for the 6-bit pwms 0 to 6. p2.1/pwm0 2 p2.2/pwm1 3 p2.3/pwm2 4 p2.4/pwm3 5 p2.5/pwm4 6 p2.6/pwm5 7 p2.7/pwm6 8 p3.0/adc0 9 port 3. 8-bit open-drain bidirectional port with alternative functions. p3.0/adc0 to p3.3/adc3 are the inputs for the software adc facility. p3.4/pwm7 is the output for the 6-bit pwm7. p3.1/adc1 10 p3.2/adc2 11 p3.3/adc3 12 p3.4/pwm7 30 v ssd 13 digital ground p0.0 14 port 0. 8-bit open-drain bidirectional port. p0.5 and p0.6 have 10 ma current sinking capability for direct drive of leds. p0.1 15 p0.2 16 p0.3 17 p0.4 18 p0.5 19 p0.6 20 p0.7 21 v ssd 22 digital ground. i.c. 23 internally connected; this pin should be connected to digital ground. i.c. 24 internally connected; this pin should be connected to digital ground. i.c. 25 internally connected; this pin should be connected to digital ground. iref 26 reference current input for analog current generator, connected to v ssa via a 27 k w resistor.
1997 jun 24 7 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 frame 27 de-interlace output synchronised with the vsync pulse to produce a non-interlaced display by adjustment of the vertical de?ection circuits. v ssd 28 internally connected; this pin should be connected to digital ground. cor 29 open-drain, active low output which allows selective contrast reduction of the tv picture to enhance a mixed mode display. rgbref 31 dc input voltage to de?ne the output high level on the rgb pins. b 32 pixel rate output of the blue colour information. g 33 pixel rate output of the green colour information. r 34 pixel rate output of the red colour information. vds 35 video/data switch push-pull output for dot rate fast blanking. hsync 36 schmitt trigger input for a ttl level version of the horizontal sync pulse; the polarity of this pulse is programmable by register bit txt1.h polarity. vsync 37 schmitt trigger input for a ttl level version of the vertical sync pulse; the polarity of this pulse is programmable by register bit txt1.v polarity. v dda 38 +5 v display power supply. v ddd 39 +5 v display power supply. oscgnd 40 crystal oscillator ground. xtalin 41 12 mhz crystal oscillator input. xtalout 42 12 mhz crystal oscillator output. reset 43 if the reset input is high for at least 3 machine cycles (36 oscillator periods) while the oscillator is running, the device is reset; this pin should be connected to v ddm via a 2.2 m f capacitor. v ddm 44 +5 v microcontroller power supply. p1.0/int1 45 port 1. 8-bit open-drain bidirectional port with alternative functions. p1.0/int1 is external interrupt 1, can be triggered on the rising/falling edge of pulse. p1.1/t0 is the counter/timer 0. p1.2/int0 is the external interrupt 0. p1.3/t1 is the counter/timer 1. p1.7/sda is the serial data port for the i 2 c-bus. p1.6/scl is the serial clock input for the i 2 c-bus. p1.1/t0 46 p1.2/int0 47 p1.3/int1 48 p1.6/scl 49 p1.7/sda 50 p1.4 51 p1.5 52 symbol pin description
1997 jun 24 8 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 7 functional description 7.1 microcontroller the functionality of the microcontroller used with this family is described with reference to the industry-standard 80c51 microcontroller. a full description of its functionality can be found in 80c51-based; 8-bit microcontrollers, data handbook ic20 . using the 80c51 as a reference, the changes made to this family fall into two categories: features not supported by the SAA5288 features found on the SAA5288 but not supported by the 80c51. 7.2 80c51 features not supported 7.2.1 i nterrupt priority the ip sfr is not implemented and all interrupts are treated with the same priority level. the normal priority of interrupts is maintained within the level. table 2 interrupts and vector address 7.2.2 o ff - chip memory the SAA5288 does not support the use of off-chip program memory or off-chip data memory. 7.2.3 i dle and p ower - down modes idle and power-down modes are not supported. consequently, the respective bits in pcon are not available. 7.2.4 uart function the 80c51 uart is not available. as a consequence the scon and sbuf sfrs are removed and the es bit in the ie sfr is unavailable. interrupt source vector address (hex) reset 000 external int0 003 timer 0 00b external int1 013 timer 1 01b byte i 2 c-bus 02b bit i 2 c-bus 053 7.3 additional features the following features are provided in addition to the standard 80c51 features. 7.3.1 i nterrupts the external int1 interrupt is modified to generate an interrupt on both the rising and falling edges of the int1 pin, when ex1 bit is set. this facility allows for software pulse-width measurement for handling of a remote control. 7.3.2 b it l evel i 2 c- bus i nterface for reasons of compatibility with the saa5290, saa5291, saa5291a and saa5491 all contain a bit level serial i/o which supports the i 2 c-bus. p1.6/scl and p1.7/sda are the serial i/o pins. these two pins meet the i 2 c-bus specification concerning the input levels and output drive capability see the i 2 c-bus and how to use it (including specifications) . consequently, these two pins have an open-drain output configuration. all the four following modes of the i 2 c-bus are supported. master transmitter master receiver slave transmitter slave receiver. three sfrs support the function of the bit-level i 2 c-bus hardware: s1int, s1bit and s1scs and are enabled by setting register bit txt8.i 2 c select to logic 0. 7.3.3 b yte l evel i 2 c- bus i nterface the byte level serial i/o supports the i 2 c-bus protocol. p1.6/scl and p1.7/sda are the serial i/o pins. these two pins meet the i 2 c-bus specification concerning the input levels and output drive capability. consequently, these two pins have an open-drain output configuration. the byte level i 2 c-bus serial port is identical to the i 2 c-bus serial port on the 8xc552. the operation of the subsystem is described in detail in the 8xc552 data sheet described in 80c51-based; 8-bit microcontrollers data handbook ic20 . four sfrs support the byte level i 2 c-bus hardware: s1con, s1sta, s1dat and s1adr. they are enabled by setting register bit txt8. i 2 c select to logic 1. 7.3.4 led support port pins p0.5 and p0.6 have a 10 ma current sinking capability to enable leds to be driven directly.
1997 jun 24 9 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 7.3.5 6- bit pwm dac s eight 6-bit dacs are available to allow direct control of analogue sections of the television. each low resolution 6-bit dac is controlled by its associated special function register (pwm0 to pwm7). the pwm outputs are alternative functions of port 2 and p3.4. the pwe bit in the sfr for the port corresponding to the pwm should be set to logic 1 for correct operation of the pwm, e.g. if pwm0 is to be used, p2.1 should be set to logic 1 setting the port pin to high-impedance. 7.3.5.1 pulse width modulator registers (pwm0 to pwm7) table 3 pulse width modulator registers (see table 10 for addresses) table 4 description of pwmn bits ( n=0to7) 76543210 pwe - pv5 pv4 pv3 pv2 pv1 pv0 bit symbol description 7 pwe if pwe is set to a logic 1, the corresponding pwm is active and controls its assigned port pin. if pwe is set to la logic 0, the port pin is controlled by the corresponding bit in the port sfr. 6 - not used 5 pv5 the output of the pwm is a pulse of period 21.33 m s with a pulse high time determined by the binary value of these 6-bits multiplied by 0.33 m s. pv5 is the most significant bit. 4 pv4 3 pv3 2 pv2 1 pv1 0 pv0
1997 jun 24 10 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 7.3.6 14- bit pwm dac one 14-bit dac is available to allow direct control of analogue sections of the television. the 14-bit pwm is controlled using special function registers tdacl and tdach. the output of the tpwm is a pulse of period 42.66 m s. the 7 most significant bits, tdach.td13 (msb) to tdach.td8 and tdacl.td7, alter the pulse width between 0 and 42.33 m s, in much the same way as in the 6-bit pwms. the 7 least significant bits, tdacl.td6 to tdacl.td0 (lsb), extend certain pulses by a further 0.33 m s, e.g. if the 7 least significant bits are given the value 01h, then 1 in 128 cycles is extended. if the 7 least significant bits are given the value 02h, then 2 in 128 cycles is extended, and so forth. the tpwm will not start to output a new value until after writing a value to tdach. therefore, if the value is to be changed, tdacl should be written to before tdach. 7.3.6.1 tpwm high byte register (tdach) table 5 tpwm high byte register (sfr address d3h) table 6 description of tdach bits 7.3.6.2 tpwm low byte register (tdacl) table 7 tpwm low byte register (sfr address d2h) table 8 description of tdacl bits 76543210 pwe - td13 td12 td11 td10 td9 td8 bit symbol description 7 pwe if pwe is set to a logic 1, the tpwm is active and controls port line p2.0. if pwe is set to a logic 0, the port pin is controlled by the corresponding bit in the port sfr. 6 - not used 5 td13 these 6-bits along with bit td7 in the tdacl register control the pulse width period. td13 is the most signi?cant bit. 4 td12 3 td11 2 td10 1 td9 0 td8 76543210 td7 td6 td5 td4 td3 td2 td1 td0 bit symbol description 7 td7 this bit is used with bits td13 to td8 in the tdach register to control the pulse width period. 6 to 0 td6 to td0 these 7-bits extend certain pulses by a further 0.33 m s.
1997 jun 24 11 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 7.3.7 s oftware adc up to 4 successive approximation adcs can be implemented in software by making use of the on-chip 8-bit dac and multiplexed voltage comparator. the software adc uses 4 analog inputs which are multiplexed with p3.0 to p3.3. table 9 adc input channel selection ch1 ch0 input pin 0 0 p3.3/adc3 0 1 p3.0/adc0 1 0 p3.1/adc1 1 1 p3.2/adc2 the control of the adc is achieved using the special function registers sad and sadb. sad.ch1 and sad.ch0 select one of the four inputs to pass to the comparator. the other comparator input comes from the dac, whose value is set by sad.sad7 (msb) to sad.sad4 and sadb.sad3 to sadb.sad0 (lsb). the setting of the value sad.sad7 to sad.sad4 must be performed at least 1 instruction cycle before the setting of sad.st to ensure comparison is made using the correct sad.sad7 to sad.sad4 value. the output of the comparator is sad.vhi, and is valid after 1 instruction cycle following the setting of sad.st to logic 1. fig.3 sad block diagram. handbook, halfpage multiplexer p3.0 p3.1 vh1 mgl115 p3.2 p3.3 ch1, ch0 sad7 to sad0 ref + ref - 1d st c1 8-bit dac
1997 jun 24 12 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 7.4 microcontroller interfacing the 80c51 communicates with the peripheral functions using special function registers which are addressed as ram locations. the registers in the teletext decoder appear as normal sfrs in the microcontroller memory map, but are written to using an internal serial bus. the sfr map is given in section 7.4.1 and the sfr bit description is given in section 7.4.2. 7.4.1 s pecial f unction r egister map table 10 special function register map; note 1 symbol name direct address (hex) bit address, symbol or alternative port function reset value (hex) 76543210 acc (2) accumulator e0 e7 e6 e5 e4 e3 e2 e1 e0 00 -------- b (2) b register f0 f7 f6 f5 f4 f3 f2 f1 f0 00 -------- dptr: data pointer (2 bytes): dph high byte 83 -------- 00 dpl low byte 82 -------- 00 ie (2)(3) interrupt enable a8 af ae ad ac ab aa a9 a8 00 ea es1 es2 * et1 ex1 et0 ex0 p0 (2) port 0 80 87 86 85 84 83 82 81 80 ff -------- p1 (2) port 1 90 97 96 95 94 93 92 91 90 ff -------- p2 (2) port 2 a0 a7 a6 a5 a4 a3 a2 a1 a0 ff -------- p3 (2)(3) port 3 b0 ---- b3 b2 b1 b0 ff -------- pcon (3) power control 87 - * - * gf1 gf0 -- 10 psw (2) program status word d0 d7 d6 d5 d4 d3 d2 d1 d0 00 cy ac f0 rs1 rs0 ov * p
1997 jun 24 13 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 pwm0 (3) pulse width modulator 0 d5 pwe * pv5 pv4 pv3 pv2 pv1 pv0 40 pwm1 (3) pulse width modulator 1 d6 pwe * pv5 pv4 pv3 pv2 pv1 pv0 40 pwm2 (3) pulse width modulator 2 d7 pwe * pv5 pv4 pv3 pv2 pv1 pv0 40 pwm3 (3) pulse width modulator 3 dc pwe * pv5 pv4 pv3 pv2 pv1 pv0 40 pwm4 (3) pulse width modulator 4 dd pwe * pv5 pv4 pv3 pv2 pv1 pv0 40 pwm5 (3) pulse width modulator 5 de pwe * pv5 pv4 pv3 pv2 pv1 pv0 40 pwm6 (3) pulse width modulator 6 df pwe * pv5 pv4 pv3 pv2 pv1 pv0 40 pwm7 (3) pulse width modulator 7 d4 pwe * pv5 pv4 pv3 pv2 pv1 pv0 40 s1adr (3) serial i 2 c-bus address db adr6 adr5 adr4 adr3 adr2 adr1 adr0 gc 00 s1con (2)(3)(4) serial i 2 c-bus control d8 df de dd dc db da d9 d8 cr2 ensi sta sto si aa cr1 cr0 00 s1scs (2)(3)(5) serial i 2 c-bus control d8 df de dd dc db da d9 d8 sdi sci clh bb rbf wbf str ens e0 s1dat (3)(4) serial i 2 c-bus data da dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 00 s1int (3)(5) serial i 2 c-bus interrupt da si ------- 7f s1sta (3)(4) serial i 2 c-bus status d9 stat4 stat3 stat2 stat1 stat0 0 0 0 f8 s1bit (3)(5) serial i 2 c-bus data d9 sdo/sdi ------- 7f symbol name direct address (hex) bit address, symbol or alternative port function reset value (hex) 76543210
1997 jun 24 14 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 sad (2)(3) software adc (msb) e8 ef ee ed ec eb ea e9 e8 00 vhi ch1 ch0 st sad7 sad6 sad5 sad4 sadb (2)(3) software adc (lsb) 98 9f 9e 9d 9c 9b 9a 99 98 00 ---- sad3 sad2 sad1 sad0 sp stack pointer 81 8f 8e 8d 8c 8b 8a 89 88 07 tcon (2) timer/counter control 88 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00 tdach tpwm high byte d3 pwe * td13 td12 td11 td10 td9 td8 40 tdacl tpwm low byte d2 td7 td6 td5 td4 td3 td2 td1 td0 00 th0 timer 0 high byte 8c th07 th06 th05 th04 th03 th02 th01 th00 00 th1 timer 1 high byte 8d th17 th16 th15 th14 th13 th12 th11 th10 00 tl0 timer 0 low byte 8a tl07 tl06 tl05 tl04 tl03 tl02 tl01 tl00 00 tl1 timer 1 low byte 8b tl17 tl16 tl15 tl14 tl13 tl12 tl11 tl10 00 tmod timer/counter mode 89 gate c/ tm1m0gatec/ tm1 m000 timer 1 timer 0 txt0 (3) teletext register 0 c0 * * auto frame * display status row only disable frame **00 txt1 (3) teletext register 1 c1 * * * * * field polarity h polarity v polarity 00 txt4 (3) teletext register 4 c4 * * east/ west disable dbl ht b mesh enable c mesh enable trans enable shadow enable 00 txt5 (3) teletext register 5 c5 bkgnd out bkgnd in cor out cor in text out text in picture on out picture on in 03 symbol name direct address (hex) bit address, symbol or alternative port function reset value (hex) 76543210
1997 jun 24 15 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 notes 1. the asterisk (*) indicates these bits are inactive and must be written to logic 0 for future compatibility. 2. sfrs are bit addressable. 3. sfrs are modified or added to the 80c51 sfrs. 4. this register is used for byte orientated i 2 c-bus, txt8. i 2 c select = 1. 5. this register is used for bit orientated i 2 c-bus, txt8. i 2 c select = 0. txt6 (3) teletext register 6 c6 bkgnd out bkgnd in cor out cor in text out text in picture on out picture on in 03 txt7 (3) teletext register 7 c7 status row top cursor on reveal t op/ bottom double height box on 24 box on 1 - 23 box on 0 00 txt8 (3) teletext register 8 c8 i 2 c select ** *****00 txt9 (3) teletext register 9 c9 cursor freeze clear memory *r4r3r2r1r000 txt10 (3) teletext register 10 ca * * c5 c4 c3 c2 c1 c0 00 txt11 (3) teletext register 11 cb d7 d6 d5 d4 d3 d2 d1 d0 00 txt12 (3) teletext register 12 cc * rom ver r4 rom ver r3 rom ver r2 rom ver r1 rom ver r0 txt on * 0xxxx x00b txt13 (2)(3) teletext register 13 b8 bf be bd bc bb ba b9 b8 00 * page clearing 525 display * * * * osd i/f busy txt16 (3) teletext register 16 cf * y2 y1 y0 * * x1 x0 00 txt17 (3) teletext register 17 b9 * * * force 625 force 525 screen col2 screen col1 screen col0 00 symbol name direct address (hex) bit address, symbol or alternative port function reset value (hex) 76543210
1997 jun 24 16 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 7.4.2 s pecial f unction r egisters bit description table 11 sfr bit descriptions register function interrupt enable register (ie) ea disable all interrupts (logic 0) or use individual interrupt enable bits (logic 1) es1 bit i 2 c-bus interrupt enable (logic 1) es2 byte i 2 c-bus interrupt enable (logic 1) et1 enable timer 1 over?ow interrupt (logic 1) ex1 enable external interrupt 1 (logic 1) et0 enable timer 0 over?ow interrupt (logic 1) ex0 enable external interrupt 0 (logic 1) power control register (pcon) gf1 general purpose ?ag 1 gf0 general purpose ?ag 0 program status word (psw) cy carry ?ag ac auxiliary carry ?ag f0 ?ag 0 rs1, rs0 register bank select control bits ov over?ow ?ag p parity ?ag 6-bit pulse width modulator control registers (pwm0 to pwm7) pwe activate this pwm and take control of respective port pin (logic 1) pv5 to pv0 binary value sets high time of pwm output serial interface slave address register (s1adr) adr6 to adr0 i 2 c-bus slave address to which the device will respond gc enables response to the i 2 c-bus general call address serial interface control register (s1con) cr2 to cr0 clock rate bits ensi i 2 c-bus interface enable sta start condition ?ag sto stop condition ?ag si interrupt ?ag aa assert acknowledge ?ag
1997 jun 24 17 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 serial interface data register (s1dat) dat7 to dat0 i 2 c-bus data serial interface status register (s1sta) - read only stat4 to stat0 i 2 c-bus interface status serial interface data register (s1bit) - read sdi i 2 c-bus data bit input serial interface data register (s1bit) - write sdo i 2 c-bus data bit output serial interface interrupt register (s1int) si i 2 c-bus interrupt ?ag serial interface control register (s1scs) - read sdi serial data input at sda sci serial clock input at scl clh clock low-to-high transition ?ag bb bus busy ?ag rbf read bit ?nished ?ag wbf write bit ?nished ?ag str clock stretching enable (logic 1) ens enable serial i/o (logic 1) serial interface control register (s1scs) - write sdo serial data output at sda sco serial clock output at scl clh clock low-to-high transition ?ag str clock stretching enable (logic 1) ens enable serial i/o (logic 1) software adc control register (sad) vhi comparator output indicating that analogue input voltage greater than dac voltage (logic 1) ch1 and ch0 adc input channel selection bits, see table 11 st initiate voltage comparison (logic 1); this bit is automatically reset to logic 0 sad7 to sad4 4 msbs of dac input value software adc control register (sadb) sad3 to sad0 4 lsbs of dac input value register function
1997 jun 24 18 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 timer/counter control register (tcon) tf1 timer 1 over?ow ?ag tr1 timer 1 run control bit tf0 timer 0 over?ow ?ag tr0 timer 0 run control bit ie1 interrupt 1 edge ?ag it1 interrupt 1 type control bit ie0 interrupt 0 edge ?ag it0 interrupt 0 type control bit 14-bit pwm msb register (tdach) pwe activate this 14-bit pwm and take over port pin (logic 1) td13 to td8 6 msbs of 14-bit number to be output by the 14-bit pwm 14-bit pwm lsb register (tdacl) td7 to td0 8 lsbs of 14-bit number to be output by the 14-bit pwm timer 0 high byte (th0) th07 to th00 8 msbs of timer 0 16-bit counter timer 1 high byte (th1) th17 to th10 8 msbs of timer 1 16-bit counter timer 0 low byte (tl0) tl07 to tl00 8 lsbs of timer 0 16-bit counter timer 1 low byte (tl1) tl17 to tl10 8 lsbs of timer 1 16-bit counter timer/counter mode control register (tmod) gate gating control c/ t counter or timer selector m1, m0 mode control bits teletext register 0 (txt0) - write only auto frame frame output switched off automatically if any video displayed (logic 1) display status row only display row 24 only (logic 1) disable frame frame output always low (logic 1) register function
1997 jun 24 19 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 teletext register 1 (txt1) - write only field polarity vsync in ?rst half of the line (logic 0) or second half of the line (logic 1) at start of even ?eld h polarity hsync input positive-going (logic 0) or negative-going (logic 1) v polarity vsync input positive-going (logic 0) or negative-going (logic 1) prd4 to prd0 page request data teletext register 4 (txt4) - write only east/ west western languages selected (logic 0) or eastern languages selected (logic 1) disable dbl hght disable display of double height teletext control codes (logic 1) in osd boxes b mesh enable enable meshing of area with black background (logic 1) c mesh enable enable meshing of area with other background colours (logic 1) trans enable set black background to transparent i.e. video is displayed (logic 1) shadow enable enable south-east shadowing (logic 1) teletext register 5 (txt5) - write only bkgnd out background colour displayed outside teletext boxes (logic 1) bkgnd in background colour displayed inside teletext boxes (logic 1) cor out cor output active outside teletext boxes (logic 1) cor in cor output active inside teletext boxes (logic 1) text out text displayed outside teletext boxes (logic 1) text in text displayed inside teletext boxes (logic 1) picture on out video picture displayed outside teletext boxes (logic 1) picture on in video picture displayed inside teletext boxes (logic 1) teletext register 6 (txt6) - write only see txt5 this register has the same meaning as txt5 but is only invoked if either news?ash (c5) or subtitle (c6) bit in row 25 of the basic page memory is set teletext register 7 (txt7) - write only status row top display row 24 below (logic 0) or above (logic 1) teletext page cursor on display cursor at location pointed to by txt9 and txt10 (logic 1) reveal display characters in areas with the conceal attribute set (logic 1) t op/bottom display rows 0 to 11 (logic 0) or 12 to 23 (logic 1) when the double height bit is set double height display each character as twice normal height (logic 1) box on 24 enable teletext boxes in memory row 24 (logic 1) box on 1-23 enable teletext boxes in memory rows 1 to 23 (logic 1) box on 0 enable teletext boxes in memory row 0 (logic 1) register function
1997 jun 24 20 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 teletext register 8 (txt8) i 2 c select select bit i 2 c-bus (logic 0) or byte i 2 c-bus (logic 1) teletext register 9 (txt9) - write only cursor freeze locks current cursor position (logic 1) clear memory write 20h into every location in display memory (logic 1) r4 to r0 memory row to be accessed by txt11 teletext register 10 (txt10) - write only c5 to c0 memory column to be accessed by txt11 teletext register 11 (txt11) d7 to d0 data byte written to, or read from display memory teletext register 12 (txt12) - read only rom ver r4 to r0 mask programmable identi?cation for character set display on power has been applied to the display hardware (logic 1) teletext register 13 (txt13) page clearing set when software requested page clear in progress 525 display set to logic 1 when 525-line syncs are driving the display osd i/f busy osd interface busy; logic 1 indicates that txt registers 0 to 16 can not currently be accessed teletext register 16 (txt16) - write only y2 to y0 sets vertical position of display area x1 to x0 sets horizontal position of display area teletext register 17 (txt17) - write only force 625 force display to 625-line mode force 525 force display to 525-line mode screen col 2 to 0 de?nes colour displayed instead of tv picture and black background register function
1997 jun 24 21 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 7.5 the display 7.5.1 i ntroduction the capabilities of the display are based on the requirements of level 1 teletext, with some enhancements for use with locally generated on screen displays. the display consists of 25 rows each of 40 characters, with the characters displayed being those from rows 0 to 24 of the basic page memory. if the txt.7 status row top bit is set row 24 is displayed at the top of the screen, followed by row 0, but normally memory rows are displayed in numerical order. the display memory stores 8-bit character codes which correspond to a number of displayable characters and control characters, which are normally displayed as spaces. the character set of the device is described in more detail in section 8. 7.5.2 c haracter matrix each character is defined by a matrix 12 pixels wide and 10 pixels high. when displayed, each pixel is 1 12 ms wide and 1 tv line, in each field, high. 7.5.3 p age attributes columns 0 to 9 of row 25 of the memory are treated by the display as if they contain display control information from teletext page headers. the bits which affect the display are shown in table 12. columns 0 to 4 are not used. if c5 (newsflash) or c6 (subtitle) is set the display uses the display mode defined in register txt6. c7 (suppress header) causes the header row (row 0) to be displayed as if every character was a space. c10 (inhibit display) displays every character on all rows as if it was a space. c12 to c14 (language control bits) cause certain character codes to be interpreted differently (see section 7.5.5). table 12 page attributes column page attribute field 76543210 50000c6c500 6 0 0 0 0 c10 0 0 c7 7 0 0 0 0 c14 c13 c12 0 8 00000000 9 00000000 fig.4 display page organisation. handbook, full pagewidth row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 09 23 mgl116 39 0 display page memory page attributes
1997 jun 24 22 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 7.5.4 e ast / west selection in common with their predecessors, these devices store teletext pages as a series of 8-bit character codes which are interpreted as either control codes (to change colour, invoke flashing etc.) or displayable characters. when the control characters are excluded, this gives an addressable set of 212 characters at any given time. more characters than this were required to give the language coverage required from the first version of the device. the txt4. east/ west bit was introduced to allow the meanings of character codes d0h to ffh to be changed, depending on where in europe the device was to be used. this bit is still used with the other language variants, although the name east/ west may not make much sense. 7.5.5 n ational option characters the interpretation of some character codes between 20h and 7fh depends on the c12 to c14 language control bits stored in row 25 of the display page. the interpretation of the c12 to c14 language control bits is dependant on the east/ west bit. 7.6 the twist attribute in many of the character sets, the twist serial attribute (code 1bh) can be used to switch to an alternative basic character code table, e.g. to change from the hebrew alphabet to the arabic alphabet on an arabic/hebrew device. for some national option languages the alternative code table is the default, and a twist control character will switch to the first code table. the display hardware on the devices allows one language to invoke the alternative code table by default when the east/ west register bit is a logic 0 and another when the bit is a logic 1. in all of the character sets defined so far, the language which invokes the alternative code table is the same for either setting of the east/ west bit. 7.6.1 o n screen display symbols in the character sets, character codes 80h to 9fh are osd symbols. an editor is available to allow these characters to be redefined by the customer. 7.6.2 l anguage group identification the devices have a readable register txt12 which contains a 5-bit identification code txt12.rom ver r4 to txt12.rom ver r0 which is intended for use in identifying which character set the device is using. 7.6.3 525- line operation when used with 525-line display syncs, the devices modify their displays such that the bottom line is omitted from each character cell. the character sets have been designed to be readable under these circumstances and anyone designing osd symbols is advised to consider this mode of operation. 7.6.4 c ontrol characters character codes 00h to 1fh, b0h to b7h and bch to bfh are interpreted as control characters which can be used to change the colour of the characters, the background colour, the size of characters, and various other features. all control characters are normally displayed as spaces. the alphanumerics colour control characters (00h to 07h) are used to change colour of the characters displayed. the graphics control characters (10h to 17h) change the colour of the characters and switch the display into a mode where the codes in columns 2, 3, 6 and 7 of the character table (see the character table above) are displayed as the block mosaic characters in columns 2a, 3a, 6a and 7a. the display of mosaics is switched off using one of the alphanumerics colour control characters. the new background character (1dh) the background colour of the display sets the background colour equal to the current foreground colour. the black background character (1ch) changes the background colour to black independently of the current foreground colour. the background colour control characters in the upper half of the code table (b0h to b7h) are additions to the normal display control characters which allow the background colour to be changed to any colour with a single control character and independently of the foreground colour. the background colour is changed from the position of the background colour control character.
1997 jun 24 23 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 displayable characters between a flash (08h) and a steady (09h) control character will flash on and off. displayable characters between a conceal display (18h) character and an alphanumerics or graphics control character are displayed as spaces, unless the txt7.reveal bit is set. the contiguous graphics (19h) and separated graphics (1ah) characters control the way in which mosaic shapes are displayed. the difference between the two is shown in fig.5. control characters encountered between a hold graphics (1eh) control character and a release graphics (1fh) control character are displayed as the last character displayed in graphics mode, rather than as spaces. from the hold graphics character until the first character displayed in graphics mode the held character is a space. the start box (0bh) and end box (0ah) characters are used to define teletext boxes. two start box characters are required to begin a teletext box, with the box starting between the 2 characters. the box ends after an end box character has been encountered. the display can be set up so that different display modes are invoked inside and outside teletext boxes e.g. text inside boxes but tv outside. this is described in section 7.6.5. the normal size (0ch), double height (0dh), double width (0eh) and double size (0fh) control characters are used to change the size of the characters displayed. if any double height (or double size) characters are displayed on a row the whole of the next row is displayed as spaces. double height display is not possible on either row 23 or row 24. the character in the position occupied by the right hand half of a double width (or double size) character is ignored, unless it is a control character in which case it takes effect on the next character displayed. this allows double width to be used to produce a display in which blank spaces do not appear when character attributes are changed. the size implying osd (bch to bfh) control characters have been included in this device to allow osd messages to be generated easily. these characters are described in full later in this document. handbook, halfpage mosaics character 7fh contiguous mosaics character 7fh separated mgl117 fig.5 contiguous and separated mosaics.
1997 jun 24 24 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 7.6.5 d isplay modes the device signals the tvs display circuits to display the r, g and b outputs of the device, rather than the video picture, by outputting a logic 1 on the vds output. the way in which this signal is switched is controlled by the bits in the txt5 and txt6 sfrs. there are 3 control functions: text on, background on and picture on. separate sets of bits are used inside and outside teletext boxes so that different display modes can be invoked. also, different sfrs are used depending on whether the newsflash (c5) or subtitle (c6) bits in row 25 of the basic page memory are set (sfr txt6) or not (sfr txt5). this allows the software to set up the type of display required on newsflash and subtitle pages (e.g. text inside boxes, tv picture outside) this will be invoked without any further software intervention when such a page is acquired. when teletext box control characters are present in the page memory, whichever is relevant of the boxes on row 0, boxes on row 1 - 23 and boxes on row 24 sfr bits in txt17 must be set if the display mode is to change in the box. these bits are present to allow boxes in certain areas of the screen to be disabled so that teletext boxes can be used for the display of osd messages without the danger of subtitles in boxes, which may also be in the page memory, being displayed. the use of teletext boxes for osd messages has been superseded in this device by the osd box concept, described later, but these bits remain to allow teletext boxes to be used, if required. the cor bits in the txt5 and txt6 sfrs control when the cor output of the device is activated (pulled-down). this output is intended to act on the tvs display circuits to reduce the contrast of the video display when it is active. the result of contrast reduction is to improve the readability of the text in a mixed text and video display. the bits in the txt5 and txt6 sfrs allow the display to be set up so that, for example, the areas inside teletext boxes will be contrast reduced when a subtitle is being displayed but that the rest of the screen will be displayed as normal video. setting the shadow txt4.shadow enable bit will add a south east shadow to the text, significantly enhancing its readability in mix mode. shadowing is shown in fig.6. the readability of text can also be enhanced using meshing. meshing causes the vds signal to switch so that when the text background colour should be displayed every other pixel is displayed from the video picture. text foreground pixels are always displayed. the txt4.bmesh bit enables meshing on areas of the screen within the text display area with black as the background colour. the txt4.cmesh bit has the same effect on areas with other background colours. meshing can only be invoked in areas displayed in text mode i.e. where the txt5.text in and txt5.bkgnd in bits are both set to logic 1, and in osd boxes. meshed text can also be shadowed. meshing is illustrated in fig.6. the txt4.trans bit causes areas of black background colour to become transparent i.e. video is displayed instead of black background. black background transparency can also only be invoked in areas displayed in text mode i.e. where the txt5.text in and txt5.bkgnd in bits are both set to logic 1, and in osd boxes. table 13 display control bits picture on text on background on effect 0 0 x text mode, black screen 0 1 0 text mode, background always black 0 1 1 text mode 1 0 x tv mode 1 1 0 mixed text and tv mode 1 1 1 text mode, tv picture outside text area
1997 jun 24 25 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 table 14 enhanced display mode selection shadow trans bmesh cmesh display 0 0 0 0 normal, unshadowed, unmeshed text 0 0 0 1 text with coloured backgrounds meshed, black background solid 0 0 1 0 text with coloured backgrounds solid, black background meshed 0 0 1 1 text with all backgrounds meshed 0 1 x 0 text with coloured backgrounds solid, black background transparent 0 1 x 1 text with coloured backgrounds meshed, black background transparent 1 0 0 1 shadowed text with coloured backgrounds meshed, black background solid 1 0 1 0 shadowed text with coloured backgrounds solid, black background meshed 1 0 1 1 shadowed text with all backgrounds meshed 1 1 x 0 shadowed text with coloured backgrounds solid, black background transparent 1 1 x 1 shadowed text with coloured backgrounds meshed, black background transparent fig.6 meshing and shadowing. handbook, halfpage meshing tv picture text foreground colour black text background colour meshing and shadowing normal mix mode se shadowing mgl118
1997 jun 24 26 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 7.7 on screen display boxes the size implying osd control characters (bch to bfh) are intended to allow osd messages to be displayed. osd boxes are not the same as teletext boxes created using the teletext boxing control characters (0ah and 0bh). when one of these characters occurs the display size changes appropriately (to normal size for bch, double height for bdh, double width for beh and double size for bfh) and an osd box starts from the next character position (set after). the osd box ends either at the end of the row of text or at the next size implying osd character. when an osd box is ended using another size implying osd character the box ends at the position of the control character (set at). this arrangement allows displays to be created without blank spaces at the ends of the osd boxes. to prevent teletext control characters from affecting the display of the osd message the flash, teletext box, conceal, separated graphics, twist and hold graphics functions are all reset at the start of an osd box, as they are at the start of the row. in order to allow the most commonly used display attributes to be set-up before the box starts the foreground colour, background colour and mosaics on/off attributes are not reset. the text within an osd box is always displayed in text mode i.e. as if the text on and bkgnd on bits are both set to a logic 1. the type of display produced inside an osd box is, therefore, dependant on the states of the txt4.shadow enable, txt4.trans enable, txt4.bmesh enable and txt4.cmesh enable register bits, as described previously. osd boxes can only be displayed in tv mode i.e. when the picture on sfr bit is a logic 1 and the text on sfr bit is a logic 0, both inside and outside text boxes and for both normal and newsflash/subtitle pages. the display of osd boxes is not affected by the c7, suppress header, and c10, inhibit display, control bits stored in row 25 of the page memory. 7.8 screen colour the register bits txt17.screen col2-0 can be used to define a colour to be displayed in place of the tv picture and the black background colour. if the bits are all set to 0, the screen colour is defined as transparent and the tv picture and background colour are displayed as normal. screen colour is displayed from 10.5 to 62.5 m s after the active edge of the hsync input and on tv lines 23 to 310 inclusive, for a 625-line display, and lines 17 to 260 inclusive for a 525-line display. when the screen colour has been redefined, no tv picture is displayed so the frame de-interlace output can be activated, if the sfr bits controlling frame are set up to allow this. table 15 screen colours 7.9 cursor if the txt7.cursor on bit is set, a cursor is displayed. the cursor operates by reversing the background and foreground colours in the character position pointed to by the active row and column bits in the txt9 and txt10 sfrs. setting the txt9.cursor freeze bit, causes the cursor to stay in its current position, no matter what happens to the active row and column positions. this means that the software can read data from the memory (e.g. top table information) without affecting the position of the cursor. screen col 2 screen col 1 screen col 0 screen colour 0 0 0 transparent 001red 0 1 0 green 0 1 1 yellow 1 0 0 blue 1 0 1 magenta 1 1 0 cyan 1 1 1 white
1997 jun 24 27 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 7.10 other display features setting the txt7.double height bit causes the normal height of all display characters to be doubled and the whole of the display area to be occupied by half of the display rows. characters normally displayed double height will be displayed quadruple height when this bit is set. rows 12 to 24 can be enlarged, rather than rows 0 to 11, by setting the txt7. top/bottom bit. this feature can be used for either a user controlled enlarge facility or to provide very large characters for the osd. the display of rows 0 to 23 can be disabled by setting the txt0.display status row only bit. the fastext prompt row (packet 24) can be displayed from the extension packet memory by setting the txt0.display x/24 bit. when this bit is set the data displayed on display row 24 is taken from row 0 in the extension packet memory. when the display from extension packet block option is enabled, the display will revert to row 24 of the basic page memory if bit 3 of the link control byte in packet 27 is set. 7.11 display timing the display synchronises to the devices hsync and vsync inputs. a typical configuration is shown in fig.7. the hsync and vsync signals are derived from the signals driving the deflection coils of the tv. locking the display to the signals from the scan circuits allows the device to give a stable display under almost all signal conditions. the polarity of the input signals which the device is expecting can be set using the txt1.h polarity and txt1.v polarity bits. if the polarity bit is a logic 0, a positive going signal is expected and if it is a logic 1, a negative going signal is expected. 7.12 horizontal timing every time an hsync pulse is received the display resynchronizes to its leading edge. to get maximum display stability, the hsync input must have fast edges, free of noise to ensure that there is no uncertainty in the timing of the signal to which the display synchronisation circuits must lock. the display area starts 17.2 m s into the line and lasts for 40 m s. the display area will be in the centre of the screen if the hsync pulse is aligned with line flyback signal. therefore, it is better to derive hsync directly from the line flyback or from an output of the line output transformer than from, say, slicing the sandcastle signal as this would introduce delays which would shift the display to the right. fig.7 timing configuration. handbook, halfpage video decoding tuner/if rgb, vds rgb cvbs mgl120 hsync, vsync frame sync circuits SAA5288 crt display
1997 jun 24 28 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 7.13 vertical timing the vertical display timing also resynchronizes to every sync pulse received. this means that the device can produce a stable display on both 625 and 525-line screens. display starts on the 41st line of each field and continues for 250 lines, or until the end of the field. normally, television displays are interlaced, i.e. only every other tv line is displayed on each field. it is normal to de-interlace teletext displays to prevent the displayed characters flickering up and down. in many tv designs this is achieved by modulating the vertical deflection current slightly in such a way that odd fields are shifted up and even fields are shifted down on the screen so that lines 1 and 314, 2 and 315 etc. are overlaid. the frame output is provided to facilitate this. if the active edge of vsync occurs in the first half of a tv line this is an even field and the frame output should be a logic 0 for this field. similarly, if vsync is in the second half of the line this is an odd field and frame should be a logic 1. the algorithm used to derive frame is such that a consistent output will be obtained no matter where the vsync signal is relative to the hsync signal, even if vsync occurs at the start and mid-points of a line. setting the txt0.disable frame bit forces the frame output to a logic 0. setting the txt0.auto frame bit causes the frame output to be active when just text is being displayed but to be forced to 0 when any video is being displayed. this allows the de-interlacing function to take place with virtually no software intervention. some tv architectures do not use the frame output but accomplish the de-interlacing function in the vertical deflection ic, under software control, by delaying the start of the scan for one field by half a line, so that lines in this field are moved up by one tv line. in such tvs, vsync may occur in the first half of the line at the start of an odd field and in the second half of the line at the start of an even field. in order to obtain correct de-interlacing in these circumstances, thetxt1.field polarity must be set to reverse the assumptions made by the vertical timing circuits on the timing of vsync in each field. the start of the display may be delayed by a line. the field polarity bit does not affect the frame output. 7.14 display position the position of the display relative to the hsync and vsync inputs can be varied over a limited range to allow for optimum tv set-up. the horizontal position is controlled by the x0 and x1 bits in sfr txt16. table 16 gives the time from the active edge of the hsync signal to the start of the display area for each setting of x0 and x1. table 16 display horizontal position the line on which the display area starts depends on whether the display is 625-line or 525-line and on the setting of the y0 to y2 bits in sfr txt16. table 17 gives the first display line for each setting of y0 to y2, for both 625 and 525-line display. on the other field, the display starts on the equivalent line. table 17 display vertical position x1 x0 hsync display ( m s) 0 0 17.2 0 1 16.2 1 0 15.2 1 1 14.2 y2 y1 y0 first line for display 625-line 525-line 0 0 0 42 28 0 0 1 44 30 0 1 0 46 32 0 1 1 48 34 1 0 0 34 20 1 0 1 36 22 1 1 0 38 24 1 1 1 40 26
1997 jun 24 29 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 fig.8 625-line display format. handbook, full pagewidth 25 rows 23 lines 250 lines 287 lines 312 lines 40 characters mgl122 40 m s 10.5 m s 52 m s 64 m s tv picture area text display area field scanning area d x d y fig.9 525-line display format. handbook, full pagewidth 25 rows 17 lines 225 lines 243 lines 263 lines 40 characters mgl123 40 m s 10.5 m s 52 m s 63.55 m s tv picture area text display area field scanning area d x d y
1997 jun 24 30 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 7.15 clock generator the oscillator circuit is a single-stage inverting amplifier in a pierce oscillator configuration. the circuitry between oscin and oscout is basically an inverter biased to the transfer point. a crystal must be used as the feedback element to complete the oscillator circuitry. it is operated in parallel resonance. oscin is the high gain amplifier input and oscout is the output. to drive the device externally oscin is driven from an external source and oscout is left open-circuit. fig.10 oscillator circuit. (1) the values of c1 and c2 depend on the crystal specification: c1 = c2 = 2c l . handbook, halfpage mlc110 oscout v ss oscin oscgnd c1 (1) c2 (1) fig.11 oscillator circuit driven from external source. handbook, halfpage mlc111 oscout oscin oscgnd external clock not connected v ss
1997 jun 24 31 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 8 character sets the two pan-european character sets are shown in figs.13 and 14. the character sets for russian, greek/turkish, arabic/english/french, thai and arabic/hebrew are available on request. 8.1 pan-european fig.12 pan-european geographical coverage. handbook, full pagewidth mgl133
1997 jun 24 32 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 handbook, full pagewidth mgl124 normal height b 3 b 2 b 1 b 0 b 4 b 5 b 6 b 7 0 1 22a3 3a4 5 6 6a 77a 8 9 c column r o w b i t s 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 a 1 0 1 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 1 1 1 e 1 1 1 0 double width hold graphics f 1 1 1 1 double size release graphics b 1 0 1 1 start box c 1 1 0 0 black back - ground d 1 1 0 1 double height new back - ground a 1 0 1 0 end box separated graphics 9 1 0 0 1 steady contiguous graphics 8 1 0 0 0 flash conceal display 7 0 1 1 1 alpha - numerics white graphics white 6 0 1 1 0 alpha - numerics cyan graphics cyan 5 0 1 0 1 alpha - numerics magenta graphics magenta 4 0 1 0 0 alpha - numerics blue graphics blue 3 0 0 1 1 alpha - numerics yellow graphics yellow 2 0 0 1 0 alpha - numerics green graphics green 0 0 0 0 0 alpha - numerics black graphics black 1 0 0 0 1 alpha - numerics red graphics red b 1 0 1 1 def 1 1 0 1 1 1 1 0 1 1 1 1 def 1 1 0 1 1 1 1 0 1 1 1 1 double width osd double size osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd osd e/w = 0 e/w = 1 osd nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt nat opt normal size osd double height osd back- ground white back- ground cyan back- ground magenta back- ground blue back- ground yellow back- ground green back- ground black back ground red osd character dependent on the language of page, refer to national option characters customer definable on-screen display character fig.13 pan-european basic character set.
1997 jun 24 33 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 fig.14 national option characters. (1) this language conforms to the ebu document sp492 or where superseded etsi document pr ets 300 706 with respect to c12/c13/c14 definition. (2) this language is included for backward compatibility with previous generation of philips teletext decoders. handbook, full pagewidth mgl125 language c12 c13 c14 000 001 010 011 100 french (1) italian (1) swedish (1) german (1) english (1) 23 24 40 5b 5c 5d 5e 5f 60 7b 7c 7d 7e character spanish (1) 10 e/w 0 111 english (2) 0 0 001 german (1) 1 010 estonian (1) 1 011 german (2) 1 100 german (2) 1 0 0 0 01 11 00 turkish (1) 00 10 101 110 11 1 1 11 rumanian (1) czech (1) serbo-croat (1) polish (1)
1997 jun 24 34 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 8.2 russian 8.3 greek/turkish fig.15 russian geographical coverage. handbook, full pagewidth mgl128 fig.16 greek/turkish geographical coverage. handbook, full pagewidth mgl129
1997 jun 24 35 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 8.4 arabic/english/french 8.5 thai fig.17 arabic/english/french geographical coverage. handbook, full pagewidth mgl131 fig.18 thai geographical coverage. handbook, full pagewidth mgl132
1997 jun 24 36 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 8.6 arabic/hebrew fig.19 arabic/hebrew geographical coverage. d book, full pagewidth mgl130
1997 jun 24 37 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 9 limiting values in accordance with the absolute maximum rating system (iec 134). note 1. this value has an absolute maximum of 6.5 v independent of v dd . 10 characteristics v dd =5v 10%; v ss =0v; t amb = - 20 to +70 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit v dd supply voltage (all supplies) - 0.3 +6.5 v v i input voltage (any input) note 1 - 0.3 v dd + 0.5 v v o output voltage (any output) note 1 - 0.3 v dd + 0.5 v i o output current (each output) - 10 ma i iok dc input or output diode current - 20 ma t amb operating ambient temperature - 20 +70 c t stg storage temperature - 55 +125 c symbol parameter conditions min. typ. max. unit supplies v dd supply voltage 4.5 5.0 5.5 v i ddm microcontroller supply current - 15 30 ma i dda analog supply current - 815 ma i ddt display supply current - 15 30 ma digital inputs reset v il low-level input voltage - 0.3 - 0.2v dd - 0.1 v v ih high-level input voltage 0.7v dd - v dd + 0.3 v i li input leakage current v i = 0 to v dd - 10 - +10 m a c i input capacitance -- 4pf hsync and vsync v th(f) switching threshold falling 0.2v dd -- v v th(r) switching threshold rising -- 0.8v dd v v hys hysteresis voltage - 0.33v dd - v c i input capacitance -- 4pf
1997 jun 24 38 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 digital outputs r, g and b; note 1 v ol low-level output voltage i ol = 2 ma 0 - 0.2 v v oh high-level output voltage i oh = - 2ma v rgbref - 0.3 v rgbref v rgbref + 0.4 v ? z o ? output impedance -- 150 w c l load capacitance -- 50 pf i o dc output current --- 4ma t r output rise time between 10 and 90%; c l =50pf -- 20 ns t f output fall time between 90 and 10%; c l =50pf -- 20 ns vds v ol low-level output voltage i ol = 1.6 ma 0 - 0.2 v v oh high-level output voltage i oh = - 1.6 ma v dd - 0.3 - v dd + 0.4 v c l load capacitance -- 50 pf t r output rise time between 10 and 90%; c l =50pf -- 20 ns t f output fall time between 90 and 10%; c l =50pf -- 20 ns r, g, b and vds t skew skew delay between any two pins -- 20 ns cor ( open - drain output ) v oh high-level pull-up output voltage -- v dd v v ol low-level output voltage i ol = 2 ma 0 - 0.5 v i ol low-level output current -- 2ma c l load capacitance -- 25 pf frame v oh high-level output voltage i ol = 8 ma 0 - 0.5 v v ol low-level output voltage i ol = - 8ma v dd - 0.5 - v dd v i ol low-level output current - 8 - +8 ma c l load capacitance -- 100 pf symbol parameter conditions min. typ. max. unit
1997 jun 24 39 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 digital input/outputs p0.0 to p0.4, p0.7, p1.0 to p1.5, p2.0 to p2.7 and p3.0 to p3.4 v il low-level input voltage - 0.3 - 0.2v dd - 0.1 v v ih high-level input voltage 0.2v dd + 0.9 - v dd + 0.3 v c i input capacitance -- 4pf v ol low-level output voltage i ol = 3.2 ma 0 - 0.45 v c l load capacitance -- 50 pf p0.5 and p0.6 v il low-level input voltage - 0.3 - 0.2v dd - 0.1 v v ih high-level input voltage 0.2v dd + 0.9 - v dd + 0.3 v c i input capacitance -- 4pf v ol low-level output voltage i ol =10ma 0 - 0.45 v c l load capacitance -- 50 pf p1.6 and p1.7 v il low-level input voltage - 0.3 - +1.5 v v ih high-level input voltage 3.0 - v dd + 0.3 v c i input capacitance -- 5pf v ol low-level output voltage i ol = 3 ma 0 - 0.5 v c l load capacitance -- 400 pf t f output fall time between 3 and 1 v -- 200 ns analog inputs iref r gnd resistor to ground - 27 - k w rgbref; note 1 v i input voltage - 0.3 - v dd v i i dc input current -- 12 ma adc0, adc1 and adc2 v il low-level input voltage - 0.3 - v dd v crystal oscillator oscin v il low-level input voltage - 0.3 - 0.2v dd - 0.1 v v ih high-level input voltage 0.7v dd - v dd + 0.3 v c i input capacitance -- 10 pf symbol parameter conditions min. typ. max. unit
1997 jun 24 40 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 notes 1. all rgb current is sourced from the rgbref pin. the maximum effective series resistance between rgbref and the r, g and b pins is 150 w . 2. crystal order number 4322 143 05561. 11 characteristics for the i 2 c-bus interface notes 1. this parameter is determined by the user software. it must comply with the i 2 c-bus specification. 2. this value gives the auto-clock pulse length which meets the i 2 c-bus specification for the special crystal frequency. alternatively, the scl pulse must be timed by software. 3. the rise time is determined by the external bus line capacitance and pull-up resistor. it must be less than 1 m s. 4. the maximum capacitance on bus lines sda and scl is 400 pf. oscout c o output capacitance -- 10 pf c rystal specification ; note 2 f xtal nominal frequency - 12 - mhz c l load capacitance - 32 - pf c1 series capacitance t amb =25 c - 18.5 - ff c0 parallel capacitance t amb =25 c - 4.9 - pf r r resonance resistance t amb =25 c - 35 -w t xtal temperature range - 20 +25 +70 c x j adjustment tolerance t amb =25 c -- 50 10 - 6 x d drift -- 30 10 - 6 symbol parameter input output i 2 c-bus specification scl timing t hd;sta start condition hold time 3 4.0 m s note 1 3 4.0 m s t low scl low time 3 4.7 m s note 1 3 4.7 m s t high scl high time 3 4.0 m s 3 4.0 m s; note 2 3 4.0 m s t rc scl rise time 1.0 m s note 3 1.0 m s t fc scl fall time 0.3 m s 0.3 m s; note 4 0.3 m s sda timing t su;dat1 data set-up time 3 250 ns note 1 3 250 ns t hd;dat data hold time 3 0 ns note 1 3 0ns t su;sta repeated start set-up time 3 4.7 m s note 1 3 4.7 m s t su;sto stop condition set-up time 3 4.0 m s note 1 3 4.0 m s t buf bus free time 3 4.7 m s note 1 3 4.7 m s t rd sda rise time 1.0 m s note 3 1.0 m s t fd sda fall time 0.3 m s 0.3 m s; note 4 0.3 m s symbol parameter conditions min. typ. max. unit
1997 jun 24 41 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 handbook, full pagewidth t rd t fd t rc t fc t hd;sta t low t high t su;dat1 t hd;dat t su;dat2 t su;dat3 0.7v dd 0.3v dd t su;sto t buf t su;sta sda (input / output) scl (input / output) start condition repeated start condition stop condition start or repeated start condition 0.7v dd 0.3v dd mlc104 fig.20 i 2 c-bus interface timing.
1997 jun 24 42 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 12 quality specifications this device will meet philips semiconductors general quality specification for business group consumer integrated circuits snw-fq-611-part e ; quality reference handbook, order number 9398 510 63011 . the principal requirements are shown in tables 18 to 20. table 18 acceptance tests per lot; note 1 table 19 processability tests (by package family); note 2 table 20 reliability tests (by process family); note 3 table 21 reliability tests (by device type) notes to table 16 to 18 1. ppm = fraction of defective devices, in parts per million. 2. ltpd = lot tolerance percent defective. 3. fpm = fraction of devices failing at test condition, in failures per million. test requirements mechanical cumulative target: <80 ppm electrical cumulative target: <80 ppm test requirements solderability <7% ltpd mechanical <15% ltpd solder heat resistance <15% ltpd test conditions requirements operational life 168 hours at t j = 150 c <1000 fpm at t j =70 c humidity life temperature, humidity, bias 1000 hours, 85 c, 85% rh (or equivalent test) <2000 fpm temperature cycling performance t stg(min) to t stg(max) <2000 fpm test conditions requirements esd and latch-up esd human body model 100 pf, 1.5 k w 2000 v esd machine model 200 pf, 0 w 200 v latch-up 100 ma, 1.5 v dd (absolute maximum)
1997 jun 24 43 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 13 application information n dbook, full pagewidth mgl126 2 v dd v dd v afc v tune v ss v ss v dd v dd v dd v dd v dd v ssd v ddm v ddd v dda v ssd v ss v ssd v ss v ss p2.1/pwm0 3 p2.2/pwm1 4 p2.3/pwm2 5 p2.4/pwm3 6 p2.5/pwm4 7 p2.6/pwm5 8 p2.7/pwm6 9 p3.0/adc0 p3.1/adc1 p3.2/adc2 p0.0 p3.3/adc3 10 11 12 13 14 15 16 17 18 19 20 21 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 g b rgbref hsync vds r vsync xtalout xtalin oscgnd p1.0/int1 reset p3.4/pwm7 iref frame i.c. i.c. i.c. 22 23 24 26 25 29 27 28 1 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 52 p2.0/tpwm a2 p1.4 p1.7/sda p1.6/scl p1.3/t1 p1.2/int0 p1.1/t0 p1.5 sda a1 scl a0 rc brightness contrast saturation hue volume (l) volume (r) v dd v dd v ss 1 k w 27 k w v dd 40 v v ss v ss v dd v ss ph2369 47 m f v dd v ss 100 nf cor v ss v dd 47 m f 100 nf 22 pf 2.2 m f v dd v ss v ss v ss eeprom pcf8582e SAA5288 ir receiver 12 mhz to tv's display circuits tv control signals field flyback line flyback fig.21 application diagram.
1997 jun 24 44 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 14 emc guidelines if possible, a ground plane under the whole ic should be present, i.e. no signal tracks running underneath the ic as shown in fig.22. the ground plane under the ic should be connected by the widest possible connection back to the ground connection of the pcb, and electrolytic decoupling capacitor. it should preferably not connect to other grounds on the way and no wire links should be present in this connection. the use of wire links increases ground bounce by introducing inductance into the ground, thereby reducing the electrolytic capacitors decoupling efficiency. the supply pins should be decoupled at the pin, to the ground plane under the ic. this is easily accomplished when using sm capacitors (which are also most effective at high frequencies). each supply pin should be connected separately to the power connection of the pcb, preferably via at least one wire link which: 1. may be replaced by a ferrite or inductor at a later point if necessary 2. will introduce a small amount of inductance. signals connected to the +5 v supply e.g. via pull-up resistors, should be connected to the +5 v supply before the wire link to the ic (i.e. not the ic side). this will prevent if from being polluted and conduct or radiate noise onto signal lines, which may then radiate themselves. oscgnd should connect only to the crystal load capacitors (and not gnd). fig.22 power supply and gnd connections for sot247-1. handbook, full pagewidth electrolytic decoupling capacitor (2 m f) wire links sm decoupling capacitors (10 to 100 nf) under-ic gnd plane ic mgl127 v ssd v ssa v ddm v ddd v dda gnd + 5 v other gnd connections under-ic gnd plane gnd connection note: no wire links
1997 jun 24 45 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 15 package outline unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot247-1 90-01-22 95-03-11 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 47.9 47.1 14.0 13.7 3.2 2.8 0.18 1.778 15.24 15.80 15.24 17.15 15.90 1.73 5.08 0.51 4.0 m h c (e ) 1 m e a l seating plane a 1 w m b 1 d a 2 z 52 1 27 26 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z e a max. 12 a min. a max. sdip52: plastic shrink dual in-line package; 52 leads (600 mil) sot247-1
1997 jun 24 46 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 16 soldering 16.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 16.2 soldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 16.3 repairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds.
1997 jun 24 47 philips semiconductors preliminary speci?cation tv microcontroller with full screen on screen display (osd) SAA5288 17 definitions 18 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 19 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca54 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 547047/00/01/pp48 date of release: 1997 jun 24 document order number: 9397 750 01856

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